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ISL6424
Data Sheet September 13, 2005 FN9175.3
Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
The ISL6424 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of two antenna ports. The device is comprised of two independent currentmode boost PWMs and two low-noise linear regulators along with the circuitry required for 22kHz tone generation, modulation and I2C device interface. The device makes the total LNB supply design simple, efficient and compact with low external component count. Two independent current-mode boost converters provide the linear regulators with input voltages that are set to the final output voltages, plus typically 1.2V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drops across each linear pass element while permitting adequate voltage range for tone injection. The final regulated output voltages are available at two output terminals to support simultaneous operation of two antenna ports for dual tuners. The outputs for each PWM are set to 13V or 18V by independent voltage select commands (VSEL1, VSEL2) through the I2C bus. Additionally, to compensate for the voltage drop in the coaxial cable, the selected voltage may be increased by 1V with the line length compensation (LLC) feature. All the functions on this IC are controlled via the I2C bus by writing 8 bits on System Register (SR, 8 bits). The same register can be read back, and two bits will report the diagnostic status. Separate enable commands sent on the I2C bus provide independent standby mode control for each PWM and linear combination, disabling the output into shutdown mode. Each output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed. The SEL18V pin allows the 13V to 18V transition with an external pin, overriding the I2C input. The ISL6424 is offered in a 32 Ld 5x5 QFN.
Features
* Single Chip Power Solution - True Dual Operation for 2-Tuner/2-Dish Applications - Both Outputs May be Enabled Simultaneously at Maximum Power - Integrated DC-DC Converter and I2C Interface * Switch-Mode Power Converter for Lowest Dissipation - Boost PWMs with > 92% Efficiency - Selectable 13V or 18V Outputs - Digital Cable Length Compensation (1V) * I2C Compatible Interface for Remote Device Control - Registered Slave Address 0001 00XX - Full 3.3V/5V Operation up to 400kHz * External Pins to Select 13V/18V Option * DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible * Built-In Tone Oscillator Factory Trimmed to 22kHz - Facilitates DiSEqC (EUTELSAT) Encoding * Internal Over-Temperature Protection and Diagnostics * Internal Overload and Overtemp Flags (Visible on I2C) * LNB Short-Circuit Protection and Diagnostics * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* LNB Power Supply and Control for Satellite Set-Top Box
References
* Tech Brief 389 (TB389) - "PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages"; Available on the Intersil website, www.intersil.com
Ordering Information
PART # * ISL6424ER PART MARKING ISL6424ER TEMP. (C) PACKAGE PKG. DWG. #
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN L32.5x5 (Pb-free) *Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6424 Pinout
ISL6424 (QFN) TOP VIEW
CPVOUT 26 CPSWIN 25 24 23 22 21 CPSWOUT TCAP2 DSQIN2 VO2 AGND VO1 DSQIN1 TCAP1 20 19 18 17 9 CS1 10 FB1 11 COMP1 12 VSW1 13 NC 14 SDA 15 ADDR 16 SCL COMP2 GATE2 VSW2
32 PGND2 CS2 SGND SEL18V1 SEL18V2 BYP PGND1 GATE1 1 2 3 4 5 6 7 8
31
30
29
28
ISL6424ER
2
VCC 27
FB2
NC
FN9175.3 September 13, 2005
Block Diagram
4 OLF1 COUNTER OVERCURRENT PROTECTION LOGIC SCHEME 1 PWM LOGIC Q S CLK1 SDA 7 PGND1 ISEL1 EN1 ENT1 ILIM1 CS AMP 9 CS1 OTF + LLC1 OLF1 OLF2 ADDR SCL ISEL2 + EN2 ENT2 LLC2 DCL ILIM2 CS AMP DCL OC1 SEL18V1 SDA ADDR SCL 14 15 16 OLF2 DCL OC2 CLK2 OVERCURRENT PROTECTION LOGIC SCHEME 2 PWM LOGIC Q S PGND2 1 COUNTER
8
GATE1
GATE2
32
10
FB1 VREF1
REF VOLTAGE ADJ1
REF VOLTAGE ADJ2 TONE INJ CKT 2
+
12
VSW1
TONE INJ CKT 1
22kHz TONE
VREF2 SEL18V2 VSW2
19
VO1 + ENT2
+ -
27
VCC SGND
ON CHIP LINEAR UVLO POR SOFT-START BYPASS DSQIN1 TCAP1 INT 5V SOFT-START EN1/EN2 ENT1 CPVOUT 26
3
DSQIN2
TCAP2
AGND
OTF
THERMAL SHUTDOWN
CHARGE PUMP
6
20
17
18
22
23
-
-
3
SLOPE COMPENSATION 11 COMP1 BAND GAP REF VOLTAGE
I2 C INTERFACE
VSEL1 CLK1 OSC. 220kHz VSEL2 CLK2
SLOPE COMPENSATION
CS2
2
COMP2 BGV +
BGV
30
/ 10 & WAVE SHAPING
ISL6424
FB2
31 5 29
VO2
21
CPSWIN
25
CPSWOUT
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24
Typical Application Schematic
VIN P1
GND
P2 E C1B 10F L1 33H R1 5.1 L3 C3 1500pF D1 + STPS2L40U C5 56F 8 7 6 5 Q1 1 2 3 4 + C1A 56F C9 E E 0.047F C2 1F C8 D 1F 17 37 38 36 35 34 6 23 TCAP1 VCC NC CPVOUT CPSWIN CPSWOUT BYP TCAP2 C10 1000pF C21 4.7F C12 1F C15A 56F
+
C15 10F L2 33H C15 E 1 2 3 4 Q2 8 7 6 5 C24 100pF E C13 1500pF R5 68K C14 33pF D2 STPS2L40U + C17 56F R6 5.1 L4 100nH C18 1F C26 1F E
E
C30 0.01F E VOUT1 P3 SP1 D3 STPS2L40U GND P4 E +5V/+3.3V P7 OUT VL C21 0.1F E
SCL SDA ADDR SGND NC AGND SEL18V1
E
16 14 15 3 13 20 4 5
4
C25 1F E 100nH C4 1F C27A 10F C27B 10F E C29 0.1F J1 SCL 1 1 GND 2 2 GND 3 3 SDA 4 4 1x4 D R12 10K
FDS6612A R2 C24 0.10 R9 100 8 9 7 11 10 12 19 18
D
FDS6612A 32 2 1 30 31 29 21 22 R10 100
R4
C28A 10F
C28B 10F
0.10 E
E C5 33pF
100pF R3 68K C7 1500pF
GATE1 CS1 PGND COMP1 FB1 VSW1 VO1 DSQIN1 33 EP
U1 ISL6424
GATE2 CS2 PGND2 COMP2 FB2 VSW2 VO2 DSQIN2 2 8V L1 SE
ISL6424
C31 0.01F E SP2 C19 0.1F E IN VL R13 100K R14 100K R16 100K R17 100K R15 100K E
P5
VOUT2
D
D4 STPS2L40U P6 GND
R11 10K R7 100 R8 100 1 2 3 4 5 6 D SW1 12 11 10 9 8 7 DISQ1 DISQ2 SEL18V1 SEL18V2 ADDR
P9 P8
SEL18V1 SEL18V2
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DIP_SW5_SPST
ISL6424
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V Logic Input Voltage Range (SDA, SCL, ENT, DSQIN 1&2, SEL18V 1&2) . . . . . . -0.5V to 7V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 32 4 Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -40C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C Operating Temperature Range . . . . . . . . . . . . . . . . . . -20C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. The device junction temperature should be kept below 150C. Thermal shut-down circuitry turns off the device if junction temperature exceeds +150C typically.
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = 25C. EN1 = EN2 = H, LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. SYMBOL TEST CONDITIONS MIN 8 EN1 = EN2 = L IIN EN1 = EN2 = LLC1 = LLC2 = VSEL1 = VSEL2 = ENT1 = ENT2 = H, No Load TYP 12 1.5 4.0 MAX 14 3.0 8.0 UNITS V mA mA
PARAMETER Operating Supply Voltage Range Standby Supply Current Supply Current UNDERVOLTAGE LOCKOUT Start Threshold Stop Threshold Start to Stop Hysteresis SOFT-START COMP Rise Time (Note 4) Output Voltage (Note 5)
7.5 7.0 350
400
7.95 7.55 500
V V mV
(Note 5) VO1 VO1 VO1 VO1 VO2 VO2 VO2 VO2 VSEL1 = L, LLC1 = L VSEL1 = L, LLC1 = H VSEL1 = H, LLC1 = L VSEL1 = H, LLC1 = H VSEL2 = L, LLC2 = L VSEL2 = L, LLC2 = H VSEL2 = H, LLC2 = L VSEL2 = H, LLC2 = H VIN = 8V to 14V; VO1, VO2 = 13V VIN = 8V to 14V; VO1, VO2 = 18V IO = 12mA to 350mA IO = 12mA to 750mA (Note 6) DCL = L, ISEL1/2 = L DCL = L, ISEL1/2 = H (Note 6)
12.74 13.72 17.64 18.62 12.74 13.72 17.64 18.62 425 775 -
512 13.0 14.0 18.0 19.0 13.0 14.0 18.0 19.0 4.0 4.0 50 100 850 900 20
13.26 14.28 18.36 19.38 13.26 14.28 18.36 19.38 40.0 60.0 80 200 550 950 -
Cycles V V V V V V V V mV mV mV mV mA mA ms ms
Line Regulation
DVO1, DVO2 DVO1, DVO2 IMAX
Load Regulation
Dynamic Output Current Limiting
Dynamic Overload Protection Off Time Dynamic Overload Protection On Time
TOFF TON
DCL = L, Output Shorted (Note 6)
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ISL6424
Electrical Specifications
VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = 25C. EN1 = EN2 = H, LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted. See software description section for I2C access to the system. (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER 22kHz TONE SECTION Tone Frequency Tone Amplitude Tone Duty Cycle Tone Rise or Fall Time LINEAR REGULATOR Drop-out Voltage
ftone Vtone dctone Tr, Tf
ENT1/2 = H ENT1/2 = H ENT1/2 = H ENT1/2 = H
20.0 500 40 5
22.0 680 50 8
24.0 800 60 14
kHz mV % s
Iout = 750mA (Note 6)
-
1.2
-
V
DSQIN PIN 1&2, SEL18V 1&2 INPUT PINs (Note 11) Asserted LOW Asserted HIGH Input Current CURRENT SENSE Input Bias Current Over Current Threshold ERROR AMPLIFIER Open Loop Voltage Gain Gain Bandwidth Product PWM Maximum Duty Cycle Minimum Pulse Width OSCILLATOR Oscillator Frequency THERMAL SHUTDOWN Temperature Shutdown Threshold Temperature Shutdown Hysteresis NOTES: 4. Internal digital soft-start. 5. VO1 for LNB1, VO2 for LNB2. Voltage programming signals VSEL1, VSEL2, LLC1, and LLC2 are implemented via the I2C bus. IO1 = IO2 = 350mA/750mA. 6. Guaranteed by design. 7. Unused DSQIN 1&2 pins should be connected to GND. SEL18V1&2 pins have 200K internal pulldown resistors. (Note 6) (Note 6) 150 20 fo Fixed at (10)(ftone) 200 220 240 kHz (Note 6) 90 93 20 % ns AOL
GBP
1.7 -
1
0.8 -
V V A
IBIAS Static current mode, DCL = H
325
700 400
500
nA mV
(Note 6) (Note 6)
70 10
88 -
-
dB MHz
6
FN9175.3 September 13, 2005
ISL6424 Typical Performance Curves
0.80 0.70 0.60 IOUT (A) 0.50 0.40 0.30 0.20 0.10 0.00 0 20 40 TEMPERATURE (C) 60 80 IOUT_max
FIGURE 1. OUTPUT CURRENT DERATING NOTE: With both channels in simultaneous operation at rated output
Functional Pin Description
SYMBOL SDA SCL VSW1, 2 Clock from I2C bus. Input of the linear post-regulator. FUNCTION Bidirectional data from/to I2C bus.
Functional Description
The ISL6424 dual output voltage regulator makes an ideal choice for advanced satellite set-top box and personal video recorder applications. Both supply and control voltage outputs for two low-noise blocks (LNBs) are available simultaneously in any output configuration. The device utilizes built-in DC/DC step-converters that, from a single supply source ranging from 8V to 14V, generate the voltages that enable the linear post-regulators to work with a minimum of dissipated power. An undervoltage lockout circuit disables the circuit when VCC drops below a fixed threshold (7.5V typ).
PGND1, 2 Dedicated ground for the output gate driver of respective PWM. CS1, 2 SGND AGND TCAP1, 2 Current sense input; connect Rsc at this pin for desired over current value for respective PWM. Small signal ground for the IC. Analog ground for the IC. Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Use this capacitor value 1F or higher. Bypass capacitor for internal 5V.
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of 22kHz in accordance with DiSEqC (EUTELSAT) standards. No further adjustment is required. The 22kHz oscillator can be controlled either by the I2C interface (ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows immediate DiSEqC data encoding separately for each LNB. (Please see Note 1 at the end of this section.) All the functions of this IC are controlled via the I2C bus by writing to the system registers (SR1, SR2). The same registers can be read back, and two bits will report the diagnostic status. The internal oscillator operates the converters at ten times the tone frequency. The device offers full I2C compatible functionality, 3.3V or 5V, and up to 400kHz operation. If the Tone Enable (ENT1/2) bit is set LOW through I2C, then the DSQIN1/2 terminal activates the internal tone signal, modulating the dc output with a 0.3V, 22kHz, symmetrical waveform. The presence of this signal usually gives the LNB information about the band to be received. Burst coding of the 22kHz tone can be accomplished due to the fast response of the DSQIN1/2 input and rapid tone response. This allows implementation of the DiSEqC (EUTELSAT) protocols.
FN9175.3 September 13, 2005
BYPASS
DSQIN1, 2 When HIGH enables internal 22kHz modulation for LNB A and LNA B respectively, Use this pin for tone enable function for LNB A and LNB B. VCC GATE1, 2 Main power supply to the chip. These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of driving the gate of a power FET. These outputs are actively held low when Vcc is below the UVLO threshold. Output voltage of LNB A and LNB B respectively. Address pin to select two different addresses per voltage level at this pin.
VO1, 2 ADDR
COMP1, 2 Error amp outputs used for compensation. FB1, 2 Feedback pins for respective PWMs
CPVOUT, Charge pump connections. CPSWIN, CPSWOUT SEL18V1, 2 When connected HIGH, this pin will change the output of the respective PWM to 18V.
7
ISL6424
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone is generated regardless of the DSQIN1/2 pin logic status for the corresponding regulator channel (LNB-A or LNB-B). The ENT1/2 bit must be set LOW when the DSQIN1 and/or DSQIN2 pin is used for DiSEqC encoding. dynamic operation can greatly reduce the power dissipation in a short circuit condition, still ensuring excellent power-on start-up in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. This can be solved by initiating any power start-up in static mode (DCL = HIGH) and then switching to the dynamic mode (DCL = LOW) after a chosen amount of time. When in static mode, the OLF1/2 bit goes HIGH when the current limit threshold at the CS pin reaches 0.45V typ and returns LOW when the overload condition is cleared. The OLF1/2 bit will be LOW at the end of initial power-on soft-start.
Linear Regulator
The output linear regulator will sink and source current. This feature allows full modulation capability into capacitive loads as high as 0.25F. In order to minimize the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. When the device is put in the shutdown mode (EN1, EN2 = LOW), both PWM power blocks are disabled. (i.e. when EN1 = 0, PWM1 is disabled, and when EN2 = 0, PWM2 is disabled). When the regulator blocks are active (EN1, EN2 = HIGH), the output can be logic controlled to be 13V or 18V (typical) by means of the VSEL bit (Voltage Select) for remote controlling of non-DiSEqC LNBs. Additionally, it is possible to increment by 1V (typical) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (LLC1/2 bit HIGH).
Thermal Protection
This IC is protected against overheating. When the junction temperature exceeds 150C (typical), the step-up converter and the linear regulator are shut off and the OTF bit of the SR is set HIGH. Normal operation is resumed and the OTF bit is reset LOW when the junction is cooled down to 135C (typical). In over temperature conditions, the OTF Flag goes HIGH and the I2C data will be cleared. The user may need to monitor the I2C enable bits and OTF flag continuously and enable the chip, if I2C data is cleared. OTF conditions may also make the OLF flags go HIGH, when high capacitive loads are present or self-heating conditions occur at higher loads.
Output Timing
The programmed output voltage rise and fall times can be set by an external capacitor. The output rise and fall times will be approximately 3400 times the TCAP value. For the recommended range of 0.47F to 2.2F, the rise and fall time would be 1.6ms to 7.6ms. Using a 0.47F capacitor insures the PWM stays below its overcurrent threshold when charging a 120F VSW filter cap during the worst case 13V to 19V transition. A typical value of 1.0F is recommended. This feature only affects the turn-on and programmed voltage rise and fall times.
External Output Voltage Selection
The output voltage can be selected by the I2C bus. Additionally, the package offers two pins (SEL18V1, SEL18V2) for independent 13V/18V output voltage selection. When using these pins, the I2C bits should be initialized to 13V status.
TABLE 1. I2C BITS 13V 14V 13V 14V SEL18V (1, 2) Low Low High High O/P VOLTAGE 13V 14V 18V 18V
Current Limiting
The current limiting block has two thresholds that can be selected by the ISEL bit of the SR and can work either statically (simple current clamp) or dynamically. The lower threshold is between 425mA and 550mA (ISEL = L), while the higher threshold is between 775mA and 950mA (ISEL = H). When the DCL (Dynamic Current Limiting) bit is set to LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shutdown for a time tOFF, typically 900ms. Simultaneously the OLF bit of the System Register is set to HIGH. After this time has elapsed, the output is resumed for a time tON = 20ms. During tON, the device output will be current limited to 425mA min. or 775mA min., depending on the ISEL bits. At the end of tON, if the overload is still detected, the protection circuit will cycle again through tOFF and tON. At the end of a full tON in which no overload is detected, normal operation is resumed and the OLF bit is reset to LOW. Typical tON + tOFF time is 920ms as determined by an internal timer. This 8
I2C Bus Interface for ISL6424
(Refer to Philips I2C Specification, Rev. 2.1) Data transmission from main microprocessor to the ISL6424 and vice versa takes place through the two wire I2C bus interface, consisting of the two lines SDA and SCL. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor. (Pull up resistors to positive supply voltage must be externally connected). When the bus is free, both lines are HIGH. The output stages of ISL6424 will have an open drain/open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100Kbps
FN9175.3 September 13, 2005
ISL6424
in the standard-mode or up to 400Kbps in the fast-mode. The level of logic "0" and logic "1" is dependent of associated value of VDD as per electrical specification table. One clock pulse is generated for each data bit transferred. The peripheral which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case, the master transmitter can generate the STOP information in order to abort the transfer. The ISL6424 will not generate the acknowledge if the POWER OK signal from the UVLO is LOW.
SCL 1 SDA MSB START SCL DATA LINE CHANGE STABLE OF DATA DATA VALID ALLOWED ACKNOWLEDGE FROM SLAVE 2 8 9
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Refer to Figure 2.
SDA
FIGURE 4. ACKNOWLEDGE ON THE I2C BUS
FIGURE 2. DATA VALIDITY
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the microprocessor can use a simpler transmission; it waits one clock without checking the slave acknowledging, and sends the new data. This approach, though, is less protected from error and decreases the noise immunity.
START and STOP Conditions
As shown in Figure 3, START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
ISL6424 Software Description
Interface Protocol
The interface protocol is comprised of the following, as shown below in Table 2: * A start condition (S)
SDA
SCL S START CONDITION P STOP CONDITION
FIGURE 3. START AND STOP WAVEFORMS
* A chip address byte (MSB on left; the LSB bit determines read (1) or write (0) transmission) (the assigned I2C slave address for the ISL6424 is 0001 00XX) * A sequence of data (1 byte + Acknowledge) * A stop condition (P)
TABLE 2. INTERFACE PROTOCOL S0 0 0 1 0 0 0 R/W ACK Data (8 bits) ACK P
Byte Format
Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (Figure 4). The peripheral that acknowledges has to pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (Of course, set-up and hold times must also be taken into account.)
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FN9175.3 September 13, 2005
ISL6424
System Register Format
* R, W = Read and Write bit * R = Read-only bit
* All bits reset to 0 at Power-On
TABLE 3. SYSTEM REGISTER 1 (SR1) R, W SR1 R, W DCL R, W ISEL1 R, W ENT1 R, W LLC1 R, W VSEL1 R, W EN1 R OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2) R, W SR2 R, W ISEL2 R, W ENT2 R, W LLC2 R, W VSEL2 R, W EN2 R OTF R OLF2
Transmitted Data (I2C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main microprocessor can write on the system registers (SR1/SR2) of the ISL6424 via I2C bus. These will be written by the microprocessor as shown below. The spare bits of SR1/SR2 can be used for other functions.
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION SR 0 0 0 0 0 0 0 0 0 0 0 0 SR 1 1 1 1 1 1 1 1 1 1 DCL X X X X X X X X X 1 0 X ISEL2 X X X X X X X 0 1 X ISEL1 X X X X X X X 0 1 X X X ENT2 X X X X X 0 1 X X X ENT1 X X X X X 0 1 X X X X X LLC2 X 0 0 1 1 X X X X X LLC1 0 0 0 1 1 X X X X X X X VSEL2 X 0 1 0 1 X X X X X VSEL1 0 0 1 0 1 X X X X X X X EN2 X 1 1 1 1 1 1 1 1 0 EN1 X 1 1 1 1 1 1 1 1 1 1 0 OTF X X X X X X X X X X OLF1 X X X X X X X X X X X X OLF2 X X X X X X X X X X SR2 is selected Vout2 = 13V, Vboost2 = 13V + Vdrop Vout2 = 18V, Vboost2 = 18V + Vdrop Vout2 = 14V, Vboost2 = 14V + Vdrop Vout2 = 19V, Vboost2 = 19V + Vdrop 22kHz tone is controlled by DSQIN2 pin 22kHz tone is ON, DSQIN2 is disabled Iout2 = 425mA max. Iout2 = 775mA max. PWM and Linear for channel 2 disabled SR1 is selected Vout1 = 13V, Vboost1 = 13V + Vdrop Vout1 = 18V, Vboost1 = 18V + Vdrop Vout1 = 14V, Vboost1 = 14V + Vdrop Vout1 = 19V, Vboost1 = 19V + Vdrop 22kHz tone is controlled by DSQIN1 pin 22kHz tone is ON, DSQIN1 is disabled Iout1 = 425mA max. Iout1 = 775mA max. Dynamic current limit NOT selected Dynamic current limit selected PWM and Linear for channel 1 disabled FUNCTION FUNCTION
NOTE: OTF and OLF1&2 are "Read Only" bits and X is a "Don't Care" for the function specified.
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ISL6424
Received Data (I2C bus READ MODE)
The ISL6424 can provide to the master a copy of the system register information via the I2C bus in read mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the following Master generated clock bits, the ISL6424 issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the MCU master can: * Acknowledge the reception, starting in this way the transmission of another byte from the ISL6424. * Not acknowledge, stopping the read mode communication. While the whole register is read back by the microprocessor, the read-only bits OLF1, OLF2, and OTF convey diagnostic information about the ISL6424. interface will not respond to any I2C commands and the system register SR1 and SR2 are initialized to all zeros, thus keeping the power blocks disabled. Once the Vcc rises above UVLO, the POWER OK signal given to the I2C interface block will be HIGH, the I2C interface becomes operative and the SRs can be configured by the main microprocessor. About 400mV of hysteresis is provided in the UVLO threshold to avoid false triggering of the PowerOn reset circuit. (I2C comes up with EN = 0; EN goes HIGH at the same time as (or later than) all other I2C data for that PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I2C interface address is 0001000, but, it is possible to choose between two different addresses simply by setting this pin at one of the two fixed voltage levels as shown in Table 8.
TABLE 6. ADDRESS PIN CHARACTERISTICS VADDR VADDR-1 "0001000" VADDR-2 "0001001" MINIMUM 0V 2.7V TYPICAL MAXIMUM 2V 5V
Power-On I2C Interface Reset
The I2C interface built into the ISL6424 is automatically reset at power-on. The I2C interface block will receive a Power OK logic signal from the UVLO circuit. This signal will go HIGH when chip power is OK. As long as this signal is LOW, the
TABLE 7. READING SYSTEM REGISTERS DCL ISEL1/2 ENT1/2 LLC1/2 VSEL1/1 EN1/2 OTF2 0 1 0 1 OLF1/2 FUNCTION TJ 130C, normal operation TJ > 150C, power blocks disabled IOUT < IMAX, normal operation IOUT > IMAX, overload protection triggered
These bits are read as they were after the last write operation.
I2C Electrical Characteristics
TABLE 8. I2C SPECIFICATIONS PARAMETER Input Logic High, VIH Input Logic Low, VIL Input Logic Current, IIL SCL Clock Frequency TEST CONDITION SDA, SCL SDA, SCL SDA, SCL; 0.4V < VIN < 4.5V 0 100kHz MINIMUM TYPICAL 0.7 x VDD 0.3 x VDD 10A 400kHz MAXIMUM
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FN9175.3 September 13, 2005
ISL6424 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 8 0.25 0.30 2.95 2.95 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.25 3.25 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9175.3 September 13, 2005

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